Packaging for semiconductor chips and related microelectronic devices may incorporate a dielectric element and terminals for connecting the chip with other electronic elements in an electronic device. As disclosed, for example, in certain embodiments of U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosures of which are hereby incorporated by reference herein, a semiconductor chip can be provided with a flexible dielectric structure having terminals thereon. The terminals on the flexible dielectric are connected to contacts on the chip by flexible leads, so that the terminals remain movable with respect to the chip. The dielectric structure may incorporate a compliant layer disposed between the terminals and the chip, which aids in mechanically decoupling the terminals from the chip. The flexible dielectric, flexible leads and compliant layer of the flexible dielectric aid in reducing stresses developed in the leads as the operation of the chip creates heat and thermal expansion within the chip and dielectric structure.
The configuration of the leads and the terminals affects the dimensions of the entire assembly. This is a concern in the semiconductor chip packaging art, as the dimensions of the assembly affects the transmission time for signals transmitted within the electronic device in which the assembly is incorporated. Delays in transmission of these signals limit the speed of operation for the electronic device. In certain embodiments taught in the '265 and '266 patents, the terminals are arranged in a "fan-in" pattern, so that the terminals are disposed over the chip itself and the size of the assembly is thereby reduced. For example, where the contacts on the chip are arranged in rows at the periphery of the chip, the terminals may be arranged on the dielectric structure overlying the central region of the chip's front surface. Electrically conductive traces may extend inwardly along the dielectric structure from the flexible outer portions of the leads to the terminals. In addition, the terminals may be arranged in a so-called "area array," i.e., an array of terminals substantially distributed over the available surface area of the dielectric structure. This maximizes the spacing between terminals for a given structure size and number of terminals, since the terminals are arranged in a two-dimensional array, as opposed to being arranged in only one or two rows.
As disclosed in the '265 and '266 patents, the terminals may be disposed either on the surface of the dielectric structure remote from the chip, or on the surface opposite the chip. For example, in the '266 patent, one embodiment uses a first dielectric layer, having a first face directed towards the chip and a second face directed away from the chip. The traces and terminals are disposed on the second face of this first layer. A further dielectric layer is provided by applying a material over the second face and the terminals and traces of the first layer. Holes or vias are then formed in the further layer to expose the terminals beneath. Conductive filler such as solder is then applied in the vias so that solder masses form bonding terminals extending over the face of the second layer remote from the chip.
In other structures, the traces and terminals may be formed on the first or chip-facing surface of a preformed dielectric layer such as a polyimide sheet and holes may be formed in the polyimide sheet in alignment with the terminals. Here again, electrically conductive terminals are deposited in the holes to form further, bonding terminals on the second surface of the dielectric structure, remote from the chip. Terminals formed from electrically conductive masses such as solder bumps and terminals designed to accommodate solder bumps are generally larger in radial dimension than the width of the traces extending from the clip. However, traces extending along the surface of the dielectric element are typically closely packed. Placement of the terminals on the dielectric layer also occupied by the traces leaves less room for the traces between the adjacent terminals. A microelectronic chip package configuration which maximizes the space available for placement of the traces, but which also allows use of relatively large terminals, would be desirable.